FIG. 1 illustrates a prior art integrated damascene structure with Cu interconnect, low-k dielectric 10, barrier metal layer 11, and oxide liner 12 formed on an insulator layer 100. The barrier metal 11, and oxide liner 12 composition of TiN, WN, or TaN, serves the purpose of preventing Cu atoms and/or ions from penetration into the low-k dielectric 10. [E. M. Zielinski, S. W. Russell, R. S. List, A. M. Wilson, C. Jin, K. J. Newton, J. P. Lu, T. Hurd, W. Y. Hsu, V. Cordasco, M. Gopikanth, V. Korthuis, W. Lee, G. Cemy, N. M. Russel, P. B. Smith, S. O'Brien, and R. H. Havemann, in Tech. Dig. IEEE Int. Electron Devices Meeting (IEDM), 936 (1997); H. Aoki, S. Yamasaki, T. Usami, Y. Tsuchiya, N. Ito, T. Onodera, Y. Hayashi, K. Ueno, H. Gomi, and N. Aoto, in Tech. Dig. IEEE Int. Electron Devices Meeting (IEDM), 777(1997); S. C. Sun, in Tech. Dig. IEEE Int. Electron Devices Meeting. (IEDM), 765 (1997); S. C. Sun, M. H. Tsai, H. T. Chiu, S. H. Chuang, and C. E. Tsai, in Tech. Dig. IEEE Int. Electron Devices Meeting. (IEDM), 61 (1995); J. P. Lu, W. Y. Hsu, J. D. Luttmer, L. K. Magel, and H. L. Tsai, J. Electrochem. Soc., 145, L21 (1998); J. P. Lu, W. Y. Hsu, G. A. Dixit, J. D. Luttmer, R. H. Havemann, and L. K. Magel,, J. Electrochem. Soc., 143, L279 (1996); Y. Huang, T. R. Yew, W. Lur, and S. W. Sun, Proc. of 15th VLSI Multilevel Interconnection Conference (VMIC), 33 (1998);] Besides, the oxide liner 12 deposited on trench sidewalls can effectively reduce the leakage current through the low-k dielectric under bias.
The resistivity of barrier metal is generally two to three orders of magnitude higher than that of copper. The barrier metal in the interconnection is obviously not beneficial to lowering the interconnect resistance. Therefore, a thin qualified barrier dielectric liner should be developed to replace both the barrier metal and the oxide liner. In other words, a damascene interconnection in a barrier-metal-free scheme by using the barrier dielectric liner can effectively minimizing the resistance-capacitance time delay [K. Mikagi, H. Ishikawa, T. Usami, M. Suzuki, K. Inoue, N. Oda, S. Chikaki, I. Sakai, and T. Kikkawa, in Tech. Dig IEEE Int. Electron Devices Meeting (IEDM), 365 (1996)], the leakage current and the process complexity.